In digital circuits, data is stored in sequential elements or storage cells. Flip flops and latches are commonly used as sequential elements, which store a data signal that they read from a data pin at a moment when a clock edge reaches the sequential element. In order to store the data signal reliably in the sequential element, the data signal is stable throughout a certain interval (setup time) and remains stable afterwards throughout another interval (hold time) before an active edge of the clock (or another form of a timing signal) reaches the sequential element.
The static delay time analysis (static timing analysis; STA) checks whether minimum time requirements relating to the hold time and the setup time are satisfied. These minimum time requirements depend on a slew of the data signal and the clock signal, the worst slew being considered in each case. These minimum requirements can also be described by a hold timing check and a setup timing check.
Here the slew of a signal corresponds to an interval that elapses until a value of the signal rises from a first specific signal value, which for example for a rising edge is 10% of the signal's maximum value, to a second specific signal value, which is greater than the first signal value and for example is 90% of the signal's maximum value. Instead of 10% and 90%, 40% and 60% are also often used for determining the slew.
If a time response of the storage cell is monotonic in relation to the data slew and the clock slew, i.e. its time response can be described by a bilinear function in relation to the data slew and the clock slew, it is sufficient in each case to consider the maximum and the minimum of the possible data and clock slews at a data and a clock input of the storage cell. In principle, any one of the four possible combinations from the minimum and maximum of the data and clock slews can yield the greatest hold timing check or setup check.
STA methods according to prior art make an assumption about which combinations they use for calculating the hold timing check or setup check. For example, Synopsis' Primetime® checks only the combination minimum data slew & minimum clock slew and the combination maximum data slew & maximum clock slew, the greatest value in each case giving the hold timing check or setup timing check calculated by Primetime. Conversely, Magma's Blastfusion® calculates the hold timing check from the combination of minimum data slew & maximum clock slew, and the setup timing check from the combination of maximum data slew & minimum clock slew. Both of these methods can generate values both too pessimistic and too optimistic in relation to the hold timing check or the setup timing check.
According to the determination of the hold timing check and setup timing check, the STA methods determine a delay of a data path and a delay of a clock path for each storage cell; this is described more precisely with the help of FIG. 1. The data path 13 is the path of the data signal, which occurs for example at a storage cell 1 on an output pin (or at a port of a microelectronic circuit). Conversely, the clock path 12 is the path of the clock, which e.g. can begin at a port, an output of a PLL or a virtual clock pin. A start of the data signal is triggered in the normal way by the clock signal. A path from an output point 14 of the clock to a clock input of the storage cell 1, at which the data path 13 begins, is denoted as data clock path 11. Conversely, a path from the output point 14 of the clock to a clock input of a storage cell 2, at which the data path 13 ends, is denoted as receive clock path 12. A combination of a particular data clock path, data path and receive clock path is called a path. It should be noted here that in real circuits, which are more complicated than the circuit specified in FIG. 1, there are usually several data paths, data clock paths and receive clock paths for each storage cell. That is, in a real circuit there are generally several data paths, which lead from the data output of the storage cell 1 or other storage cells or input ports (which are not shown in FIG. 1) to the data input of the storage cell 2.
To determine a time response for a digital circuit, a hold time difference or a hold time skew and a setup time difference or a setup time skew are calculated according to the following formulae (1), (2):Hold time difference=Data delay−Clock delay−Hold time check  (1)Setup time difference=Clock delay−Data delay−Setup timing check  (2)
The data delay in equation (1) is the minimum delay of all possible data paths for the particular storage cell, and the clock delay is the maximum delay of all possible receive clock paths for the particular storage cell. Conversely, in equation (2) the clock delay is the minimum delay of all possible receive clock paths for the particular storage cell, and the data delay is the maximum delay of all possible data clock paths for the particular storage cell.
In the calculation of the check, the data and clock slews are used, which are propagated in each case over all possible corresponding data paths, data clock paths and receive clock paths up to the data and clock input. In relation to the selection of which slews (caused by different timing arcs) should be propagated by the cells and crosspoints, various methods already known in prior art can be applied.
The hold time difference and setup time difference calculated with the equations (1) and (2) can be positive or negative. A negative hold time difference or setup time difference means that a hold time condition or setup time condition has been violated, i.e. it cannot be guaranteed that the corresponding data signal will be reliably saved in the corresponding storage cell. A difference of 0 sec means no violation yet of the hold time difference or the setup time difference, but it is probable that such a violation then occurs in a real circuit (in silicon).
In order for the determination of the time response for a digital circuit to return a correct result, both the hold timing check and the setup timing check must be correctly determined. This is not achieved by methods according to prior art, as previously explained, and consequently the methods according to prior art do not return a correct result for the time response of a digital circuit, or at least not always.